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JAECE .,   Volume(5) - Issue(1), 2019
pp 1-9,   https://dx.doi.org/10.18831/djece.org/2019011001

FPGA Implementation of Reduced Complexity LDPC Codes

N Murali Krishna;

Abstract

Error detection is the process of detecting an error for the purpose of reliable communication between transmitter and receiver. This paper proposes an Error Control Coding (ECC) technique in flash memories using FPGA implementation. Due to several advantages, NAND based Multi-Level Cell (MLC) flash memory is used in this paper. In flash memories, there is an increased amount of soft errors and thus the encoder and decoder circuits of this memory must be protected. For this purpose, fault tolerant system based on Low Density Parity Check (LDPC) product code scheme is introduced. The main requirement of this scheme is to reduce the area. These product code scheme uses LDPC code for performing encoding operation and thus the designed fault tolerant system for flash memories is implemented using the programming language Verilog HDL, and the area covered can also be synthesized using the software XILINX ISE. The obtained synthesis result proves that the hardware complexity of this fault tolerant system of MLC NAND based flash memory is reduced.

Keywords

ECC, FPGA, MLC, LDPC, Memories.

Received
20/02/2018
, Accepted
11/10/2018
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