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JAECE .,   Volume(4) - Issue(2), 2018
pp 1-10,   http://dx.doi.org/10.18831/djece.org/2018021001

FPGA Implementation of On-Chip Network

N Murali Krishna;

Abstract

This paper presents the design of 32 bit UART (Universal Asynchronous Receiver Transmitter) RISC (Reduced Instruction Set Computing) processor with dynamic power management system to minimize power consumption and transmission cost. Coarse grained architecture is suggested due to its innumerable advantages over fine grained architecture. Coarse Grained Arrays (CGAs) with run-time re-configurability play a challenging task to design Network on-Chip (NoC) communication systems satisfying the power and area of embedded system. The proposed architecture is implemented on FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language), and the obtained comparison power graph signifies that it consumes less power when compared to BETA RISC processor.

Keywords

Coarse grained architecture, RISC processor, UART, Network on-chip, FPGA implementation.

Received
20/02/2018
, Accepted
23/04/2018
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