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Research Article

Year : 2018 | Volume: 4 | Issue: 1 | Pages: 1-8

Linear Interpolation Algorithms and their Architectures for Image Scaling A Survey

C John Moses1*, D Selvathi, G Shaya Edal Queen2

http://dx.doi.org/doi:10.18831/djece.org/12018011001

Corresponding author

C John Moses*

Associate Professor, Dept. of ECE, Sreyas Institute of Engineering and Technology, Hyderabad, India.

  • 1. Associate Professor, Dept. of ECE, Sreyas Institute of Engineering and Technology, Hyderabad, India.

Received on: 2017/08/30

Revised on: 2017/11/16

Accepted on: 2017/12/04

Published on: 2017/12/21

  • Linear Interpolation Algorithms and their Architectures for Image Scaling A Survey, C John Moses, D Selvathi, G Shaya Edal Queen 2017/12/21, DJ Journal of Advances in Electronics and Communication Engineering, 4(1), 1-8, http://dx.doi.org/10.18831/djece.org/12018011001.

    Published on: 2017/12/21

Abstract

Image interpolation is the process of increasing the number of pixels in an image such that the image is enlarged. Interpolation is commonly called as image upscaling, image zooming or image magnification. Linear Interpolation (LI) is fast, cost effective and has low power consumption. It also provides a better image quality. It requires only two pixels to calculate the interpolated pixel value. Applications of LI include computer graphics, medical imaging, remote sensing and multimedia applications (e.g. video teleconferencing). In this survey, various types of LI algorithms and their hardware architectures are analyzed and compared. These algorithms are implemented for different Very Large Scale Integrated Circuit (VLSI) based implementations such as Field Programmable Gate Array (FPGA) and Complementary Metal Oxide Semiconductor (CMOS) technologies. These interpolation algorithms are compared with respect to various parameters like Peak Signal to Noise Ratio (PSNR) and gate count. Based on the evaluation, it is observed that Adder Based Stepwise linear Interpolation (ABSI) method provides better image quality with reduced chip area.

Keywords

Scaling, Linear interpolation, Pixel, Peak signal to noise ratio, Gate count.